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SmartASIC, Inc.
SD1210
DATA SHEET
SD1210
Dual-Interface SXGA TFT LCD Display Controller
November 1999
November, 1999 Revision B
SmartASIC Confidential
1
SmartASIC, Inc.
SD1210
SD1210 DATA SHEET DAT-SD1210-1199-B
November 1999
Document DAT-SD1210-1099-A DAT-SD1210-1199-B
Revisions SD1210 Data Sheet - A SD1210 Data Sheet - B
Date October 1999 November 1999
Copyright 1999, SmartASIC, Inc. All Right Reserved SmartASIC, Inc. reserves the right to change or modify the information contained herein without notice. It is the customer's responsibility to ensure he/she has the most recent revision of the user guide. SmartASIC, Inc. makes no warranty for the use of its products and bears no responsibility for any error or omissions, which may appear in this document.
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SD1210
1. OVERVIEW
The SD1210 is enhanced version of the SD1200 chip. It is an IC designed for dualinterface SXGA TFT LCD monitors. A dual-interface LCD monitor takes analog or digital RGB signals from a graphic card of a personal computer, the exact same input interface as a conventional CRT monitor. This feature makes a dual-interface LCD monitor a true replacement for a conventional CRT monitor. The analog input RGB signals are first sampled by six channels of 8-bit A/D converters, and the 48-bit RGB data are then fed into the SD1210. For digital interface, the input data are first received by a TMDS receiver, and the 24/48 bit RGB output data of TMDS receiver are then fed into the SD1210. The SD1210 is capable of performing automatic detection of the display resolution and timing of input signals generated from various PC graphic cards. No special driver is required for the timing detection, nor any manual adjustment. The SD1210 then automatically scales the input image to fill the full screen of the LCD monitor. The SD1210 can interface with TFT LCD panels from various manufacturers by generating either 24-bit or 48-bit RGB signal to the LCD panel based upon the timing parameters saved in the EEPROM. The SD1210 implements four advanced display technologies: 1. Advanced mode detection and auto-calibration without any external CPU assist 2. Advanced programmable interpolation algorithm 3. Stand-alone mode support, and 4. Advanced true color support with both dithering and frame modulation. The SD1210 also provides distinguished system features to the TFT LCD monitor solution. The first one is "plug-and-play", and the second one is "cost-effective system solution". To be truly plug-and-display, the SD1210 performs automatic input mode detection and auto phase calibration, so the LCD monitor can ensure that the A/D converters' sample clock is precisely synchronized with the input video data, and to preserve the highest image bandwidth for the highest image quality. Furthermore, the SD1210 can generate output video even when the input signal is beyond the specifications or no input signal is fed. For "cost-effective system solution", the SD1210 implements many system support features such as OSD mixer, error status indicators, 2-wire serial interface for both EEPROM and host CPU interface, and low-cost IC package. Another important contributing factor is that the SD1210 does not require external frame buffer memory for the automatic image scaling and synchronization. Figure 1 shows the block diagram of the SD1210 as well as the connections of important system components around the SD1210.
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Figure 1: SD1210 Functional Block Diagram
SD1210
ADC
Phase Control
Input Mode Detection & Auto Calibration
Buffer Memory
Scaling Interpolation Dithering
Write Control
Read Control
OSD Mixer
TFT LCD Monitor
Input PLL
CPU Interface
E2ROM Interface
CPU
Output PLL
E2PROM
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SD1210
2. PIN DESCRIPTION
Figure 2: SD1210 package diagram
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Table 1: SD1210 pin description (sorted by pin number)
Symbol B_IN10 B_IN11 B_IN12 B_IN13 DATA_SEL PIN Number 1 2 3 4 5 I/O I I I I I
SD1210
B_IN14 B_IN15 B_IN16 B_IN17 ROM_SCL ROM_SDA GND CPU_SCL CPU_SDA PWM_CTL CLK_1M VDD CLK_1M_O RESET_B R_OSD G_OSD B_OSD EN_OSD
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCAN_EN TEST_EN VCLK01 FCLK0 VCLK00 FCLK1 VCLK1 HSYNC_O VSYNC_O DCLK_OUT DE_OUT GND VDD R_OUT0_E November, 1999 Revision B
24 25 26 27 28 29 30 31 32 33 34 35 36 37
Description Channel B Data Input Color Blue (LSB) Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue Indicate Channel A or Channel B contains valid input data: 1: data in Channel A is valid 0: data in Channel B is valid I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Channel B Data Input Color Blue I Channel B Data Input Color Blue (MSB) O SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface Ground I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface O PWM control signal (Detail description in PWM Operation Section) I Free Running Clock (default: 1MHz) Power Supply O Feedback of free Running Clock I System Reset ( active LOW) I OSD Color Red I OSD Color Green I OSD Color Blue I OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times } I Manufacturing test pin (NC) I Manufacturing test pin (NC) I Input Clock 1 O Input PLL Feedback Clock I Input Clock 0 O Output PLL Feedback Clock I Output PLL Output Clock O Output HSYNC (the polarity is programmable through CPU, default is active low) O Output VSYNC (the polarity is programmable through CPU, default is active low) O Output Clock to Control Panel (the polarity is programmable through CPU) O Output Display Enable for Panel (the polarity is programmable through CPU, default is active HIGH) Ground Power Supply O Output Color Red Even Pixel (left pixel) 6
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R_OUT1_E R_OUT2_E R_OUT3_E HSYNC_X VSYNC_X GND R_OUT4_E VDD VDD R_OUT5_E GND R_OUT6_E R_OUT7_E GND R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O VDD R_OUT4_O R_OUT5_O R_OUT6_O R_OUT7_O GND G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E G_OUT4_E VDD G_OUT5_E G_OUT6_E G_OUT7_E GND GND G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O VDD G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O GND GND B_OUT0_E B_OUT1_E B_OUT2_E B_OUT3_E B_OUT4_E B_OUT5_E November, 1999 Revision B 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 O O O O O O
SD1210
O O O O O O O O O O O O O O O O O O O
O O O O O O O O
O O O O O O
Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Default HSYNC generated by ASIC (active LOW) Default VSYNC generated by ASIC (active LOW) Ground Output Color Red Even Pixel (left pixel) Power Supply Power Supply Output Color Red Even Pixel (left pixel) Ground Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Ground Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Power Supply Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Ground Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Power Supply Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Ground Ground Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Power Supply Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Ground Ground Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) 7
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B_OUT6_E VDD VDD B_OUT7_E GND B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O VDD B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O GND R_IN00 R_IN01 R_IN02 R_IN03 VDD R_IN04 R_IN05 R_IN06 R_IN07 R_IN10 R_IN11 GND R_IN12 R_IN13 VDD R_IN14 R_IN15 R_IN16 R_IN17 GND G_IN00 G_IN01 G_IN02 G_IN03 VDD G_IN04 G_IN05 ADC_CLK0 G_IN06 G_IN07 GND G_IN10 G_IN11 ADC_CLK1 G_IN12 G_IN13 VDD November, 1999 Revision B 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 O Output Color Blue Even Pixel (left pixel) Power Supply Power Supply Output Color Blue Even Pixel (left pixel) Ground Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Power Supply Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Ground Channel A Data Input Color Red (LSB) Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Power Supply Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red (MSB) Channel B Data Input Color Red (LSB) Channel B Data Input Color Red Ground Channel B Data Input Color Red Channel B Data Input Color Red Power Supply Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red (MSB) Ground Channel A Data Input Color Green (LSB) Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Power Supply Channel A Data Input Color Green Channel A Data Input Color Green Sample Clock for ADC 0 Channel A Data Input Color Green Channel A Data Input Color Green (MSB) Ground Channel B Data Input Color Green (LSB) Channel B Data Input Color Green Sample Clock for ADC 1 Channel B Data Input Color Green Channel B Data Input Color Green Power Supply
SD1210
O O O O O O O O O I I I I I I I I I I I I I I I I I I I I I I O I I I I O I I
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G_IN14 G_IN15 G_IN16 G_IN17 GND B_IN00 B_IN01 B_IN02 VDD B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 GND HSYNC_I VSYNC_I DE_IN VDD 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I I I I I I I I I I I I I I I Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green (MSB) Ground Channel A Data Input Color Blue (LSB) Channel A Data Input Color Blue Channel A Data Input Color Blue Power Supply Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue (MSB) Ground Input HSYNC (any polarity) Input VSYNC (any polarity) DE input for digital interface Power Supply
SD1210
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Table 2: SD1210 pin description (sorted by function)
Symbol R_IN00 R_IN01 R_IN02 R_IN03 R_IN04 R_IN05 R_IN06 R_IN07 R_IN10 R_IN11 R_IN12 R_IN13 R_IN14 R_IN15 R_IN16 R_IN17 G_IN00 G_IN01 G_IN02 G_IN03 G_IN04 G_IN05 G_IN06 G_IN07 G_IN10 G_IN11 G_IN12 G_IN13 G_IN14 G_IN15 G_IN16 G_IN17 B_IN00 B_IN01 B_IN02 B_IN03 B_IN04 B_IN05 B_IN06 B_IN07 B_IN10 B_IN11 B_IN12 B_IN13 B_IN14 B_IN15 B_IN16 B_IN17 November, 1999 Revision B PIN Number 105 106 107 108 110 111 112 113 114 115 117 118 120 121 122 123 125 126 127 128 130 131 133 134 136 137 139 140 142 143 144 145 147 148 149 151 152 153 154 155 1 2 3 4 6 7 8 9 I/O I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Description Channel A Data Input Color Red (LSB) Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red Channel A Data Input Color Red (MSB) Channel B Data Input Color Red (LSB) Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red Channel B Data Input Color Red (MSB) Channel A Data Input Color Green (LSB) Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green Channel A Data Input Color Green (MSB) Channel B Data Input Color Green (LSB) Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green Channel B Data Input Color Green (MSB) Channel A Data Input Color Blue (LSB) Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue Channel A Data Input Color Blue (MSB) Channel B Data Input Color Blue (LSB) Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue Channel B Data Input Color Blue (MSB)
SD1210
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DATA_SEL 5 I
SD1210
Indicate Channel A or Channel B contains valid input data: 1: data in Channel A is valid 0: data in Channel B is valid Input HSYNC (any polarity) Input VSYNC (any polarity) DE input for digital interface Sample Clock for ADC 0 Sample Clock for ADC 1
HSYNC_I VSYNC_I DE_IN ADC_CLK0 ADC_CLK1
157 158 159 132 138
I I I O O
R_OUT0_E R_OUT1_E R_OUT2_E R_OUT3_E R_OUT4_E R_OUT5_E R_OUT6_E R_OUT7_E R_OUT0_O R_OUT1_O R_OUT2_O R_OUT3_O R_OUT4_O R_OUT5_O R_OUT6_O R_OUT7_O G_OUT0_E G_OUT1_E G_OUT2_E G_OUT3_E G_OUT4_E G_OUT5_E G_OUT6_E G_OUT7_E G_OUT0_O G_OUT1_O G_OUT2_O G_OUT3_O G_OUT4_O G_OUT5_O G_OUT6_O G_OUT7_O B_OUT0_E B_OUT1_E B_OUT2_E B_OUT3_E B_OUT4_E November, 1999 Revision B
37 38 39 40 44 47 49 50 52 53 54 55 57 58 59 60 62 63 64 65 66 68 69 70 73 74 75 76 78 79 80 81 84 85 86 87 88
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Even Pixel (left pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Red Odd Pixel (right pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Even Pixel (left pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Green Odd Pixel (right pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) 11
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B_OUT5_E B_OUT6_E B_OUT7_E B_OUT0_O B_OUT1_O B_OUT2_O B_OUT3_O B_OUT4_O B_OUT5_O B_OUT6_O B_OUT7_O HSYNC_O VSYNC_O DCLK_OUT DE_OUT 89 90 93 95 96 97 98 100 101 102 103 31 32 33 34 O O O O O O O O O O O O O O O Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Even Pixel (left pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel) Output Color Blue Odd Pixel (right pixel)
SD1210
Output HSYNC (the polarity is programmable through CPU, default is active low) Output VSYNC (the polarity is programmable through CPU, default is active low) Output Clock to Control Panel (the polarity is programmable through CPU) Output Display Enable for Panel (the polarity is programmable through CPU, default is active HIGH) Input Clock 1 Input PLL Feedback Clock Input Clock 0 Output PLL Feedback Clock Output PLL Output Clock
VCLK01 FCLK0 VCLK00 FCLK1 VCLK1 ROM_SCL ROM_SDA CPU_SCL CPU_SDA PWM_CTL CLK_1M CLK_1M_O RESET_B HSYNC_X VSYNC_X R_OSD G_OSD B_OSD EN_OSD
26 27 28 29 30 10 11 13 14 15 16 18 19 41 42 20 21 22 23
I O I O I
O SCL in I2C for EEPROM interface I/O SDA in I2C for EEPROM interface I SCL in I2C for CPU interface I/O SDA in I2C for CPU interface O I O I O O I I I I PWM control signal (Detail description in PWM Operation Section) Free Running Clock (default: 1MHz) Feedback of free Running Clock System Reset ( active LOW) Default HSYNC generated by ASIC (active LOW) Default VSYNC generated by ASIC (active LOW) OSD Color Red OSD Color Green OSD Color Blue OSD Mixer Enable =0, No OSD output =1,R_OUT[7:0]= {R_OSD repeat 8 times} G_OUT[7:0]= {G_OSD repeat 8 times } B_OUT[7:0]= {B_OSD repeat 8 times }
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SCAN_EN TEST_EN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 24 25 17 36 45 46 56 67 77 91 92 99 109 119 129 141 150 160 12 35 43 48 51 61 71 72 82 83 94 104 116 124 135 146 156 I I Manufacturing test pin (NC) Manufacturing test pin (NC) Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Power Supply Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
SD1210
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SD1210
3. FUNCTIONAL DESCRIPTION
The SD1210 has the following major function blocks: 1. Input mode detection and auto calibration block 2. Buffer memory and read/write control block 3. Image scaling, interpolation and dithering block 4. OSD mixer and LCD interface block 5. EEPROM interface block 6. CPU interface block The following sections will describe the functionality of these blocks.
3.1.
3.1.1.
Input mode detection & auto calibration block
Supported input modes
SD1210 can handle up to 14 different input modes. For SD1210, an input mode is defined by its horizontal resolution with its vertical resolution. The input modes with the same horizontal and vertical resolution but with different frame rates are still considered as one single input mode. In the default EEPROM setup, SD1210 accepts the following eleven input video modes: 1. 640 x 350 2. 640 x 400 3. 720 x 400 4. 640 x 480 (VGA) 5. 800 x 600 (SVGA) 6. 832 x 624 (MAC) 7. 1024 x 768 (XGA) 8. 1152 x 864 9. 1152 x 870 10. 1280 x 960 11. 1280 x 1024 (SXGA) Users can easily change the definitions of the acceptable input modes by adjusting the values in the appropriate EEPROM entries. There is no frame rate restriction on the input modes. However, since the output signal is synchronized with the input signal at the same refresh rate, the input refresh rate has to be within the acceptable range of the LCD panel. The user-defined video modes can be defined by storing appropriate timing information in the EEPROM. Detail definitions of the EEPROM entries are described
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in Section 3.5.2. 3.1.2. Input mode detection and frequency detection
SD1210
The SD1210 can automatically detect the mode of the input signal without any user adjustment or driver running on the PC host or external CPU. This block automatically detects polarity of input synchronization and the sizes of back porch, valid data window and the synchronization pulse width in both vertical and horizontal directions. The size information is then used not only to decide the input resolution, to generate the frequency divider for the input PLL, to lock the PLL output clock with HSYNC, but also to automatically scale the image to full screen and to synchronize the output signal with the input signal. The detection logic is always active to automatically detect any changes to the input mode. Users can manually change the input mode information at run time through the CPU interface. Detailed operation of the CPU interface is described in Section 3.6. "CPU Interface". Mode detection and frequency detection can be independently turned ON or OFF by the external CPU. This feature allows system customers to have better control of the mode-detection and frequency detection process. When the detection is turned OFF, the external CPU can change the input mode and frequency definitions. 3.1.3. Phase calibration
The SD1210 can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of the input signal and to get the best quality. The SD1210 implements a proprietary image quality function. During the auto-calibration process, the SD1210 continues to search for the best phase to optimize the image quality. The output image may display some jitter and blurring during the auto-calibration process, and the image will become crisp and sharp once the optimum phase is found. User can change the sampling clock phase value through the external CPU. Detailed operation of the CPU interface is described in Section 3.6. "CPU Interface". The phase calibration process can be delayed and even disabled by the external CPU if the system designer wants to have his/her own implementation. The phase calibration can be independently turned ON or OFF by the external CPU. When the calibration is turned OFF, the external CPU can change the input mode and frequency definitions. 3.1.4. PWM operation
The SD1210 implements a unique algorithm to adjust the phase of the A/D converter's sampling clock. An external delay circuit is required to compliment the SD1210 for the phase-calibration process. The SD1210 generates a Pulse-Width Modulated (PWM) signal to the external delay circuit. The delay circuit should insert
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SD1210
a certain amount of time delay synchronization pulse based upon the width of the PWM signal. A brief circuit diagram for the PWM is shown in Figure 3. The PWM signal from the SD1210 is a periodical signal with a period that is 1023 times the period of the free-running clock connected to the pin "CLK_1M". System manufacturers may select any frequency for the free running clock. The default clock frequency is 1MHz. System manufacturers also decide the unit delay for the external delay circuit. The delay information is stored in the EEPROM. When the SD1210 wants to delay the synchronization pulse for N units of delay, it will output the PWM with the high time equal to (N * the period of the free-running clock), and with low time equal to (1023-N)* the period of the free-running clock. When N=1023, the PWM signal stays high all the time, and when N=0, the PWM signal is always low. Figure 3: SD1210 PWM circuitry block diagram
SD1210
PWM Delay Circuitry
Ref_Clk
PLL
Synchronization pulse
3.1.5.
Free Running Clock
As described in previous section, a free-running clock is needed for the SD1210. This clock is used for many of the SD1210's internal operations. PWM operation is one of them. System manufacturers can select the frequency of the free-running clock, and the default clock frequency is 1MHz. System manufacturers can use an oscillator to generate the free-running clock, and feed that clock directly to the pin "CLK_1M", or use a crystal connecting to "CLK_1M" and "CLK_1M_O".
3.2.
Buffer memory and read/write control block
The SD1210 uses internal buffer memory to store a portion of the input image for image scaling and output synchronization. No external memory buffer is needed for the SD1210. The write control logic ensures the input data are stored into the right area of the buffer memory, and the read control logic is responsible to fetch the data from the buffer memory from the correct area and at the correct timing sequence. With the precise timing control of the write and read logic, the output image is
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SD1210
appropriately scaled to the full screen, and the output signal is perfectly synchronized with the input signals.
3.3.
Image scaling, interpolation and dithering block
The SD1210 supports both automatic image scaling and interpolation. 3.3.1. Image scaling
The SD1210 supports several different input modes, and the input image may have different sizes. It is essential to support automatic image scaling so that the input image is always displayed to the full screen regardless the input mode. The SD1210 scales the images in both horizontal and vertical directions. It calculates the correct scaling ratio for both directions based upon the LCD panel resolution and the input mode and timing information produced by the "Input mode detection & auto calibration" block. The scaling ratio is re-adjusted whenever a different input mode is detected. The ratio is then fed to the buffer memory read control logic to fetch the image data with the right sequence and timing. Some of the image data may be read more than once to achieve the scaling effect. 3.3.2. Image interpolation
The SD1210 supports image interpolation to achieve better image quality. A basic image scaling algorithm replicates the input images to achieve the scaling effect. The replication scheme usually results in a poor image quality. The SD1210 implements a proprietary interpolation algorithm to improve the image quality. The programmable interpolation is implemented with a 256-entry mapping table in the EEPROM to allow system users to adjust the bi-linear interpolation parameters to control the sharpness and smoothness quality of the image. In the default setting, the mapping table contains a straight line of slope equal to 1, i.e. the data in entry N equal to the value N. If the mapping table contains a line of slope equal to 2, then the output image will be a bit sharper than the image generated by a table with the default setting. Through an external microcontroller, users can chose among different interpolation algorithm. 3.3.3. Dithering
The SD1210 supports 16.7 million true colors for a 6-bit panel. Two dithering algorithms are implemented and users can chose between them through the external microcontroller. The first one is area-based dithering, and the second one is a framebased frame modulation, which also is called frame rate control. Through the external microcontroller, users can choose among different dithering algorithms.
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3.3.4. Text Enhancement
SD1210
In order to generate a good picture, the SD1210 incorporate a proprietary scheme to detect text and non-text picture. Then applying the appropriate process to improve the text image based on the detection of incoming source. By using the text enhancement function correctly, the text image will be looked more pleasant and near perfect after scaled up or down. Users can achieve a preferred image by changing the settings in "text control" register. 3.3.5. Sharpness Enhancement
No matter how many times the original image got enlarged or shrunk by the internal interpolator. With the embedded powerful DSP arrays, SD1210 always can enhance the overall image sharpness (edge) to different degree for the various requirements. The sharpness can be adjusted bi-directionally which means either going sharper or softer to certain point set by the user. It's easy to activate the sharpness enhancement by program "sharpness control" register.
3.4.
OSD mixer and LCD interface
At the output stage, the SD1210 performs the OSD mixer function, and then generates the 24-bit / 48-bit RGB signal to the LCD panel with the correct timing. 3.4.1. OSD mixer
In the OSD mixer block, the SD1210 mixes the normal output RGB signal with the OSD signal. The OSD output data is generated based on the "R_OSD", "G_OSD" and "B_OSD" pins as well as the "OSD Intensity" data in EEPROM entry. When the "EN_OSD" is active high, the OSD is active, and the SD1210 will send the OSD data to the LCD panel. The OSD has 16 different color schemes based on the combinations of the three OSD color pins and the "OSD Intensity" data. When R_OSD=1, and OSD_Intensity=0, the SD1010 will output 128 to the output red channel, R_OUT. When R_OSD=1 and OSD_Intensity=1, the SD1210 will output 255. The same scheme is used for G_OSD to G_OUT and for B_OSD to B_OUT. As part of the mixer control function, the SD1210 implements three mixing control registers, "OSD R Weight" (38H), "OSD G Weight"(39H), and "OSD B Weight" (3AH). The mixing equation is shown below:
R_OUT = (R_OSD) * (OSD R Weight/255) + R * (1 - OSD R Weight/255) G_OUT = (G_OSD) * (OSD G Weight/255) + G * (1 - OSD G Weight/255) B_OUT = (B_OSD) * (OSD B Weight/255) + B * (1 - OSD B Weight/255)
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When the weight is 255, the OSD output will overlay on top of the normal output. When the weight is 0, the OSD output is disabled. 3.4.2. LCD interface
The SD1210 support both 24- and 48-bit RGB interfaces with SXGA LCD panels from various panel manufacturers. The LCD panel resolution and timing information is stored in the external EEPROM. The information in the EEPROM includes timing related to the output back porch, synchronization pulse width and valid data window. The timing information is used to generate the frequency divider for the output PLL, to lock the PLL output clock with HSYNC for the LCD data clock, and to synchronize the output VSYNC and input VSYNC.
3.5.
EEPROM interface
As mentioned in previous sections, the external EEPROM stores crucial information for the SD1210 internal operations. The SD1210 interfaces with the EEPROM through a 2-wire serial interface. The suggested EEPROM device is an industry standard serial-interface EEPROM (24x08). The 2-wire serial interface scheme is briefly described here and a detailed description can be found in public literature. 3.5.1. 2-wire serial interface
The 2-wire serial interface uses 2 wires, SCL and SDA. The SCL is driven by the SD1210 and used mainly as the sampling clock. The SDA is a bi-directional signal and used mainly as a data signal. Figure 4 shows the basic bit definitions of the 2-wire serial interface. The 2-wire serial interface supports random and sequential read operations. Figures 5 and 6 show the data sequences for random read and sequential read operations.
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Figure 4: START, STOP AND DATA Definitions in 2-wire serial interface
SD1210
SDA
SCL
START DATA CHANGE
DATA STABLE DATA CHANGE
STOP
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SD1210
Figure 5: Data sequence for read access (both single and multiple bytes)
S T A R T S AT CO KP
DEVICE ADDRESS [6:0]
W RA IC TK E
WORD ADDRESS [5:0]
A C K
S T O P
S T A R T
DEVICE ADDRESS [6:0]
RA EC AK D
DATA READ
M S B B I T
6
L SR B /_ W B I T 0
M S B B I T
M S B B I T
L S B B I T 0
M S B B I T
L S B B I T 0
7
6
7
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Figure 6: Data sequence for write access (both single and multiple bytes)
S T A R T W RA IC TK E S T AO C P K
DEVICE ADDRESS [6:0]
WORD ADDRESS [5:0]
A C K
DATA n
A C K
DATA n+x
M S B B I T
L R S /_ B W B I T 0
M S B B I T
M S B B I T
L S B B I T 0
M S B B I T
L S B B I T 0
6
7
7
7
3.5.2.
EEPROM Contents
The contents of EEPROM are primarily dependent on the specifications of the LCD panel. SmartASIC provides suggested EEPROM contents for LCD panels from various panel manufacturers. The section presents all the entries in the EEPROM, and briefly describes their definitions. This allows the system manufacturers to have their own EEPROM contents to distinguish their monitors. The EEPROM contents can be partitioned into 15 parts. The first 14 parts are input mode dependent. When the SD1210 detects the input mode, it will then load the information related to the detected mode from the EEPROM. The information in the 15th part is mainly for input mode detection as well as some threshold values for error status indicators. In the default setting, the SD1210 is set to recognize the following eleven modes: 640x350, 640x400, 720x400, 640x480, 800x600, 832x624, 1024x768, 1152x864, 1152x870, 1280x960, and 1280x1024 modes. Then the EEPROM will be partitioned as follows:
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SD1210
* * * * * * * * * * * * * * *
Part 1: mode 1: 640x350 mode (in default setting) Part 2: mode 2: 640x400 mode (in default setting) Part 3: mode 3: 720x400 mode (in default setting) Part 4: mode 4: 640x480 mode (in default setting) Part 5: mode 5: 800x600 mode (in default setting) Part 6: mode 6: 832x624 mode (in default setting) Part 7: mode 7: 1024x768 mode (in default setting) Part 8: mode 8: 1152x864 mode (in default setting) Part 9: mode 9: 1152x970 mode (in default setting) Part 10: mode 10: 1280x960 mode (in default setting) Part 11: mode 11: 1280x1024 mode (in default setting) Part 12: mode 12 Part 13: mode 13 Part 14: mode 14 Part 15: input mode detection and scaling related parameters
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Part 1-14: Input Mode Dependent Data
Symbol Width (bits) 11 11 11 11 11 11 11 11 11 12 4 Address For 640x350 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H [6:3] Description
VPW VBP VBP Source Target Skip Pixel VSIZE HPW HBP HSIZE HTOTAL HTOTAL Source Line Expansion Pixel Expansion H. Fog Factor H. Fog Factor V. Fog Factor V. Fog Factor Minimum Input lines [10:8] Maximum Input pixels [10:8] Minimum input lines [7:0]
LCD VSYNC pulse width LCD VSYNC back porch (including VPW) LCD VSYNC back porch (source equivalent) = VBP * Line Expansion and round up If VBP can not be converted into source evenly, the leftover is converted into number of pixels LCD number of lines LCD HSYNC pulse width LCD HSYNC back porch (including HPW) LCD number of columns LCD total number of pixels per line including all porches LCD total number of clocks per line (source equivalent) = HTOTAL/Line Expansion Vertical source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-15: expansion ratio other than one-to-one (expansion) Horizontal source-to-destination scaling factor 0: one-to-one expansion (no expansion) 1-7: expansion ratio other than one-to-one (expansion) Horizontal fogging factor high byte Horizontal fogging factor low byte Vertical fogging factor high byte Vertical fogging factor low byte Upper 3 bits of minimum input lines Upper 3 bits of maximum input pixels Minimum input lines = (VSIZE + VBP)* Line Expansion When the input has fewer lines than this value, it is considered as an ERROR, and INPUT_X status bit will be HIGH. Maximum input pixels per line. Auto clock recovery will not set input PLL divisor larger than this value. Source horizontal size upper 3 bits Source vertical size upper 3 bits 24
3
14H [2:0]
8 8 8 8 3
15H[7:0] 16H[7:0] 17H[7:0] 18H[7:0] 19H[6:4]
3 8
19H[2:0] 1AH
Maximum input pixels [7:0] Source HSIZE[10:8] Source November, 1999 Revision B
8
1BH
3 3
1CH [6:4] 1CH [2:0]
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VSIZE[10:8] Source HSIZE[7:0] Source VSIZE[7:0] Check sum
SD1210
8 8 8
1DH 1EH 1FH
Source horizontal size lower 8 bits Source vertical size lower 8 bits Sum of above 31 bytes (keep lower 8 bits only)
Mode 640x400 720x400 640x480 800x600 832x624 1024x768 1152x864 1152x870 1280x960 1280x1024 User define Mode 1 User define Mode 2 User define Mode 3
Address Range 20H 3FH 40H 5FH 60H 7FH 80H 9FH A0H BFH C0H DFH E0H FFH 100H 11FH 120H 13FH 140H 15FH 160H 17FH 180H 19FH 1A0H 1BFH
Part 15: Input Mode Detection Data
Symbol Control byte 0 Width (bits) 8 Address 200H Description
Control byte 1
8
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Bit 6 - bit 0 : device ID for external CPU access Bit 7: 0: select internal generated H/V SYNC 1: select external input H/V SYNC 201H Bit0: 0: disable automatic input gain control 1: enable automatic input gain control Bit1: 0: enable input H/V SYNC polarity control (make input SYNC positive polarity) 1: bypass input H/V SYNC polarity control SmartASIC Confidential
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SD1210
Control byte 2
8
202H
Bit2: 0: single pixel input 1: dual pixel input Bit3: 0: disable digital input 1: enable digital input Bit4: 0: YUV input format is unsigned (128 offset) 1: YUV input format is signed Bit5: 0: RGB input for video mode 1: YUV input for video mode Bit6: 0: disable video input 1: enable video input Bit7: 0: disable decimation support 1: enable decimation Bit 0: 0: don't invert input odd/even field indicator 1: invert input odd/even field indicator Bit 1: 0: disable half clock mode for dual pixel input 1: enable half clock mode for dual pixel input Bit 2: 0: disable BY2 for auto calibration 1: enable BY 2 for auto calibration Bit 3: 0: disable BY4 for auto calibration 1: enable BY 4 for auto calibration Bit 4: 0: disable BY8 for auto calibration 1: enable BY 8 for auto calibration Bit7-5: output clock phase adjustment, larger number gives larger phase delay.
Mode 640x350 Sync Polarity Res0 threshold [10:8] Res0 threshold [7:0] Mode 640x400 Sync Polarity Res1 threshold [10:8] Res1 threshold [7:0] Mode 720x400 Sync Polarity Res2 threshold [10:8] Res2 threshold [7:0] Mode 640x480 Sync Polarity Res3 threshold [10:8] Res3 threshold [7:0] Mode 800x600 Sync Polarity Res4 threshold [10:8] Res4 threshold November, 1999 Revision B
2 3 8 2 3 8 2 3 8 2 3 8 2 3 8
203H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 203H[2:0] Upper bound of the line number for 640x350 mode Upper bound of the line number for 640x350 mode, and lower bound for 640x400 205H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 205H[2:0] Upper bound of the line number for 640x400 mode Upper bound of the line number for 640x400 mode, and lower bound for 720x400 207H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 207H[2:0] Upper bound of the line number for 720x400 mode Upper bound of the line number for 720x400 mode, and lower bound for 640x480 209H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 209H[2:0] Upper bound of the line number for 640x480 mode Upper bound of the line number for 640x480 mode, and lower bound for 800x600 20BH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 20BH[2:0] Upper bound of the line number for 800x600 mode 20CH Upper bound of the line number for 800x600 mode, and 26 20AH 208H 206H 204H
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[7:0] Mode 832x624 Sync Polarity Res5 threshold [10:8] Res5 threshold [7:0] Mode 1024x768 Sync Polarity Res6 threshold [10:8] Res6 threshold [7:0] Mode 1152x864 Sync Polarity Res7 threshold [10:8] Res7 threshold [7:0] Mode 1152x870 Sync Polarity Res8 threshold [10:8] Res8 threshold [7:0] Mode 1280x960 Sync Polarity Res9 threshold [10:8] Res9 threshold [7:0] Mode 1280x1024 Sync Polarity Res10 threshold [10:8] Res10 threshold [7:0] Reserve mode 1 Sync Polarity Reserve mode 1 Res threshold [10:8] Reserve mode 1 Res threshold [7:0] Reserve mode 2 Sync Polarity Reserve mode 2 Res threshold [10:8] Reserve mode 2 Res threshold [7:0] Reserve mode 3 Sync Polarity Reserve mode 3 Res threshold [10:8] November, 1999 Revision B
SD1210
2 3 8 2 3 8 2 3 8 2 3 8 2 3 8 2 3 8 2 3 8 2 3 8 2 3
lower bound for 832x624 20DH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 20DH[2:0] Upper bound of the line number for 832x624 mode Upper bound of the line number for 832x624 mode, and lower bound for 1024x768 20FH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 20FH[2:0] Upper bound of the line number for 1024x768 mode Upper bound of the line number for 1024x768 mode, and lower bound for 1152x864 211H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 211H[2:0] Upper bound of the line number for 1152x864 mode. Upper bound of the line number for 1152x864 mode, and lower bound for 1152x870 213H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 213H[2:0] Upper bound of the line number for 1152x870 mode. Upper bound of the line number for 1152x870 mode, and lower bound for 1280x960. 215H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 215H[2:0] Upper bound of the line number for 1280x960 mode. Upper bound of the line number for 1280x960 mode, and lower bound for 1280x1024. 217H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 217H[2:0] Upper bound of the line number for 1280x1024 mode. 218H Upper bound of the line number for 1280x1024 mode. 216H 214H 212H 210H 20EH
219H[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 219H[2:0] Resolution threshold for reserve mode 1 21AH Resolution threshold for reserve mode 1
21BH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 21BH[2:0] Resolution threshold for reserve mode 2 21CH Resolution threshold for reserve mode 2
21DH[5:4] The polarity of input synchronization signals. Bit 0 is for VSYNC and bit 1 is for HSYNC 21DH[2:0] Resolution threshold for reserve mode 3
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Reserve mode 3 Res threshold [7:0] Enable SYNC Check 8 14 21EH Resolution threshold for reserve mode 3
SD1210
Maximum VBP Mode0 vertical size Mode1 vertical size Mode2 vertical size Mode3 vertical size Mode4 vertical size Mode5 vertical size Mode6 vertical size Mode7 vertical size Mode8 vertical size Mode9 vertical size Mode10 vertical size Mode11 vertical size Mode12 vertical size Mode0 horizontal size Mode1 horizontal size Mode2 horizontal size Mode3 horizontal size Mode4 horizontal size Mode5 horizontal size Mode6 horizontal size Mode7 horizontal size Mode8 horizontal size Mode9 horizontal size Mode10 horizontal size Mode11 horizontal size Mode12 horizontal size Data low threshold
8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 8
Data high threshold
8
Edge threshold Calibration mode
8 2
21FH-220H Enable SYNC polarity check during input mode detection. 1: enable SYNC polarity based mode detection 0: disable SYNC polarity based mode detection bit 0: 640x350 bit 1: 640x400 bit 2: 720x400 bit 3: 640x480 bit 4: 800x600 bit 5: 832x624 bit 6: 1024x768 bit 7: 1152x864 bit 8: 1152x870 bit 9: 1280x960 bit 10: 1280x1024 bit 11: res mode1 bit 12: res mode2 bit 13: res mode3 221H The maximum vertical back porch for input video 222H-223H Mode0 vertical size for digital input 224H-225H Mode1 vertical size for digital input 226H-227H Mode2 vertical size for digital input 228H-229H Mode3 vertical size for digital input 22AH-22BH Mode4 vertical size for digital input 22CH-22DH Mode5 vertical size for digital input 22EH-22FH Mode6 vertical size for digital input 230H-231H Mode7 vertical size for digital input 232H-233H Mode8 vertical size for digital input 234H-235H Mode9 vertical size for digital input 236H-237H Mode10 vertical size for digital input 238H-239H Mode11 vertical size for digital input 23AH-23BH Mode12 vertical size for digital input 23CH-23DH Mode0 horizontal size for digital input 23EH-23FH Mode1 horizontal size for digital input 240H-241H Mode2 horizontal size for digital input 242H-243H Mode3 horizontal size for digital input 244H-245H Mode4 horizontal size for digital input 246H-247H Mode5 horizontal size for digital input 248H-249H Mode6 horizontal size for digital input 24AH-24BH Mode7 horizontal size for digital input 24CH-24DH Mode8 horizontal size for digital input 24EH-24FH Mode9 horizontal size for digital input 250H-251H Mode10 horizontal size for digital input 252H-253H Mode11 horizontal size for digital input 254H-255H Mode12 horizontal size for digital input 256H Low water mark for valid data. If the data is smaller than this threshold, it is considered LOW internally 257H High water mark for valid data. If the data is larger than this threshold, it is considered HIGH internally 258H Minimum difference between the data value of two adjacent pixels to be considered as an edge 259H [1:0] Selects different operation modes of internal phase calibration. The selection criterion is as follows: 0: when input video signal has large overshot, it results in longest calibration time 1: when input video signal has median overshot, it results in long calibration time 2: when input video signal has normal overshot, SmartASIC Confidential 28
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SD1210
PWM unit delay
16
25AH-25BH
Maximum link off time
22
25CH-25EH
Maximum refresh rate
16
25FH-260H
Maximum input frequency
8
261H
Minimum pixels per line for LCD LCD polarity
11 4
262H-263H
it results in normal calibration time (recommended) 3: when input video signal has no overshot, it results in shortest calibration time The unit delay used in the external PWM delay circuitry. If the free-running clock is 1MHz, and the intended unit delay is 0.2 ns (= 5,000MHz), then a value of 5,000MHz/1MHz = 5,000 is used here. Maximum time when input VSYNC is off before the LINK_DWN pin turns ON (unit: clock period of the free running clock). If the free-running clock is 1MHz, and the intended maximum time is 1 second, then a value of 1,000,000 s/ 1 s = 1,000,000 is used here. Maximum refresh rate supported by the LCD panel. If the intended maximum refresh rate is 75Hz, and the free-running clock is 1MHz, then a value of 1000000/75=133,333 is used here Maximum source clock rate supported by the SD1010 (unit: frequency of free-running clock). If the intended maximum clock rate is 60MHz, and the free-running clock is 1MHz, then a value of 60 is used here. If the input signal has a higher frequency than this value, the VCLK0_X status bit will turn ON. Minimum number of pixels per line for LCD panel
Output enable for output pin 51-54, 56-59, 61-64, 66-69, 71-74, 76-79, 8184, 86-89, 91-97, 99, 101-104, 106-109 Driving capability control for output pin 51-54, 56-59, 61-64, 6669, 71-74, 76-79, 81-84, 86-89, 91-97, 99, 101104, 106-109
1
264H[3:0] Controls the polarity of output VSYNC, HSYNC, clock and display enable:Bit0: 0: clock active high, 1: clock active low Bit1: 0: HSYNC active low, 1: HSYNC active high Bit2: 0: VSYNC active low, 1: VSYNC active high Bit4: 0: de active high, 1: de active low 265H[3] Enable for programmable output pad: 1: output is enabled 0: output is tri-state
3
Output enable for output pin 49 (DE) Driving capability control for output pin 49 (DE)
1
3
265H[2:0] 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA 266H[7] Enable for programmable output pad: 1: output is enabled 0: output is tri-state 266H[6:4] 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA SmartASIC Confidential 29
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SD1210
Output enable for output pin 46 (HSYNC_O) Driving capability control for output pin 46 (HSYNC_O)
1
266H[3]
3
266H[2:0]
Output enable for output pin 49 (VSYNC_O) Driving capability control for output pin 49 (VSYNC_O)
1
267H[7]
3
267H[6:4]
Output enable for output pin 46 (DCLK_OUT) Driving capability control for output pin 46 (DCLK_OUT)
1
267H[3]
3
267H[2:0]
Extension right
4
268H[7:4]
Extension left
4
268H[3:0]
Extension down
2
269H[1:0]
Gamma_format0
24
26AH-26CH
Gamma_format1
24
26DH-26FH
Gamma_th0_r Gamma_th1_r Gamma_th2_r Gamma_th3_r November, 1999 Revision B
8 8 8 8
270H 271H 272H 273H
6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Enable for programmable output pad: 1: output is enabled 0: output is tri-state 0: 2mA 1: 6mA 2: 6mA 3: 10mA 4: 4mA 5: 8mA 6: 8mA 7: 12mA Numbers of pixels extended right for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification Numbers of pixels extended left for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification Numbers of lines extended down for support of non-full screen expansion for secondary resolution to avoid exceeding panel specification 26AH: gamma_format0_red 26BH: gamma_format0_green 26CH: gamma_format0_blue 26DH: gamma_format1_red 26EH: gamma_format1_green 26FH: gamma_format1_blue Gamma_threshold0 for red Gamma_threshold1 for red Gamma_threshold2 for red Gamma_threshold3 for red 30
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Gamma_th4_r Gamma_th5_r Gamma_th6_r Gamma_th0_g Gamma_th1_g Gamma_th2_g Gamma_th3_g Gamma_th4_g Gamma_th5_g Gamma_th6_g Gamma_th0_b Gamma_th1_b Gamma_th2_b Gamma_th3_b Gamma_th4_b Gamma_th5_b Gamma_th6_b Gamma_scale0_r Gamma_scale1_r Gamma_scale2_r Gamma_scale3_r Gamma_scale4_r Gamma_scale5_r Gamma_scale6_r Gamma_scale7_r Gamma_scale0_g Gamma_scale1_g Gamma_scale2_g Gamma_scale3_g Gamma_scale4_g Gamma_scale5_g Gamma_scale6_g Gamma_scale7_g Gamma_scale0_b Gamma_scale1_b Gamma_scale2_b Gamma_scale3_b Gamma_scale4_b Gamma_scale5_b Gamma_scale6_b Gamma_scale7_b Gamma_offset0_r Gamma_offset1_r Gamma_offset2_r Gamma_offset3_r Gamma_offset4_r Gamma_offset5_r Gamma_offset6_r Gamma_offset7_r Gamma_offset0_g Gamma_offset1_g Gamma_offset2_g November, 1999 Revision B 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 274H 275H 276H 277H 278H 279H 27AH 27BH 27CH 27DH 27EH 27FH 280H 281H 282H 283H 284H 285H 286H 287H 288H 289H 28AH 28BH 28CH 28DH 28EH 28FH 290H 291H 292H 293H 294H 295H 296H 297H 298H 299H 29AH 29BH 29CH 29DH 29EH 29FH 2A0H 2A1H 2A2H 2A3H 2A4H 2A5H 2A6H 2A7H Gamma_threshold4 for red Gamma_threshold5 for red Gamma_threshold6 for red Gamma_threshold0 for green Gamma_threshold1 for green Gamma_threshold2 for green Gamma_threshold3 for green Gamma_threshold4 for green Gamma_threshold5 for green Gamma_threshold6 for green Gamma_threshold0 for blue Gamma_threshold1 for blue Gamma_threshold2 for blue Gamma_threshold3 for blue Gamma_threshold4 for blue Gamma_threshold5 for blue Gamma_threshold6 for blue Gamma_scalefactor0 for red Gamma_scalefactor1 for red Gamma_scalefactor2 for red Gamma_scalefactor3 for red Gamma_scalefactor4 for red Gamma_scalefactor5 for red Gamma_scalefactor6 for red Gamma_scalefactor7 for red Gamma_scalefactor0 for green Gamma_scalefactor1 for green Gamma_scalefactor2 for green Gamma_scalefactor3 for green Gamma_scalefactor4 for green Gamma_scalefactor5 for green Gamma_scalefactor6 for green Gamma_scalefactor7 for green Gamma_scalefactor0 for blue Gamma_scalefactor1 for blue Gamma_scalefactor2 for blue Gamma_scalefactor3 for blue Gamma_scalefactor4 for blue Gamma_scalefactor5 for blue Gamma_scalefactor6 for blue Gamma_scalefactor7 for blue Gamma_offset0 for red Gamma_offset1 for red Gamma_offset2 for red Gamma_offset3 for red Gamma_offset4 for red Gamma_offset5 for red Gamma_offset6 for red Gamma_offset7 for red Gamma_offset0 for green Gamma_offset1 for green Gamma_offset2 for green
SD1210
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Gamma_offset3_g Gamma_offset4_g Gamma_offset5_g Gamma_offset6_g Gamma_offset7_g Gamma_offset0_b Gamma_offset1_b Gamma_offset2_b Gamma_offset3_b Gamma_offset4_b Gamma_offset5_b Gamma_offset6_b Gamma_offset7_b Check sum 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2A8H 2A9H 2AAH 2ABH 2ACH 2ADH 2AEH 2AFH 2B0H 2B1H 2B2H 2B3H 2B4H 2B5H
SD1210
Gamma_offset3 for green Gamma_offset4 for green Gamma_offset5 for green Gamma_offset6 for green Gamma_offset7 for green Gamma_offset0 for blue Gamma_offset1 for blue Gamma_offset2 for blue Gamma_offset3 for blue Gamma_offset4 for blue Gamma_offset5 for blue Gamma_offset6 for blue Gamma_offset7 for blue Sum of all part 9 bytes (keep only lower 8 bit)
3.6.
CPU interface
The SD1210 supports a 2-wire serial interface to an external CPU. The interface allows the external CPU to access and modify control registers inside the SD1210. The 2-wire serial interface is similar to the EEPROM interface, and the CPU is the host that drives the SCL all the time as the clock and for "start" and "stop" bits. The SCL frequency can be as high as 5MHz. The SDA is a bi-directional data wire. This interface supports random and sequential write operations for the CPU to modify one or multiple control registers, and random and sequential read operations for the CPU to read all or part of the control registers. The default device ID for the SD1210 is fixed "1111111". The device ID can be programmed through EEPROM entry 200H bit 0 through bit 6. This avoids any conflict with other 2-wire serial devices on the same bus. The following table briefly describes the SD1210 control registers. The external CPU can read these registers to know the state of the SD1210 as well as the result of input mode detection and phase calibration. The external CPU can modify these control registers to disable several SD1210 features and force the SD1210 into a particular state. When the CPU modifies the control registers, the new data will be first stored in a set of shadow registers, and then copied into the actual control registers when the "CPU Control Enable" bit is set. When the "CPU Control Enable" bit is set, the external CPU will retain control and the SD1210 will not perform the auto mode detection and auto calibration. The external CPU is able to adjust the size of the output image and move the output image up and down by simply changing the porch size and pixel and line numbers of the input signal. These adjustments can be tied to the external user control button on the monitor.
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SD1210
A set of four control registers are used to generate output signal when there is no input signal available to the SD1210 or the input signal is beyond the acceptable ranges. This operation mode is called standalone mode, which is very important for the end users when they accidentally select an input mode beyond the acceptable range of the SD1210 or when the input cable connection becomes loose for any reason. System manufacturers can display appropriate OSD warning messages on the LCD panel to notify the users about the problem. Table 3: SD1210 Control Registers
Symbol VBP Source VSIZE Source VTOTAL Source HBP Source HSIZE Source HTOTAL Source Mode Source Width 11 11 11 11 11 11 4 Mode RW RW RW RW RW RW RW Address 0H-1H 2H-3H 4H-5H 6H-7H 8H-9H AH-BH CH[3:0] Description Input VSYNC back porch (not include pulse width) Input image lines per frame Input total number of lines including porches Input HSYNC back porch (not include pulse width) Input image pixels per line Input total number of pixels per line including porches Input video format 0: 640x350 1: 640x400 2: 720x400 3: 640x480 4: 800x600 5: 832x624 6: 1024x768 7: user defined mode 1 8: user defined mode 2 9: user defined mode 3 10: user defined mode 4 11: user defined mode 5 12: user defined mode 6 13: user defined mode 7 14-15: error Input sampling clock phase For standalone mode, the pulse width of VSYNC For standalone mode, total number of line per frame For standalone mode, HSYNC active time in s For standalone mode, HSYNC cycle time in s Disable auto calibration for this mode: 1: disable 0: enable The number of frames need to be skipped before starting auto calibration for this mode
Clock Phase Source VPW standalone VTOTAL standalone HPW standalone HTOTAL standalone Disable auto calibration for mode 640x350 Delay auto calibration for mode 640x350 Disable auto calibration for mode 640x400 Delay auto calibration for mode 640x400 Disable auto November, 1999 Revision B
10 11 11 11 11 1
RW RW RW RW RW RW
DH-EH FH-10H 11H-12H 13H-14H 15H-16H 17H[7]
15
RW
17H[6:0]18H 19H[7]
1
RW
15
RW
Disable auto calibration for this mode: 1: disable 0: enable 19H[6:0]- The number of frames need to be skipped before 1AH starting auto calibration for this mode 1BH[7] Disable auto calibration for this mode: 33
1
RW
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calibration for mode 720x400 Delay auto calibration for mode 720x400 Disable auto calibration for mode 640x480 Delay auto calibration for mode 640x480 Disable auto calibration for mode 800x600 Delay auto calibration for mode 800x600 Disable auto calibration for mode 832x624 Delay auto calibration for mode 832x624 Disable auto calibration for mode 1024x768 Delay auto calibration for mode 1024x768 Disable auto calibration for mode INVALID Delay auto calibration for mode INVALID Bypass Sync Polarity
SD1210
15
RW
1: disable 0: enable 1BH[6:0]- The number of frames need to be skipped before 1CH starting auto calibration for this mode Disable auto calibration for this mode: 1: disable 0: enable 1DH[6:0]- The number of frames need to be skipped before 1EH starting auto calibration for this mode Disable auto calibration for this mode: 1: disable 0: enable 1FH[6:0]- The number of frames need to be skipped before 20H starting auto calibration for this mode Disable auto calibration for this mode: 1: disable 0: enable 21H[6:0]- The number of frames need to be skipped before 22H starting auto calibration for this mode Disable auto calibration for this mode: 1: disable 0: enable 23H[6:0]- The number of frames need to be skipped before 24H starting auto calibration for this mode Disable auto calibration for this mode: 1: disable 0: enable 25[6:0]- The number of frames need to be skipped before 26H starting auto calibration for this mode 27H[7] Bypass Input SYNC polarity detection (default 0): 1: bypass input SYNC polarity detection 0: detect input SYNC polarity and make them negative polarity Enable dithering for 6-bit panel (default 0): 1: enable dithering 0: disable dithering *also check register Control_C[6] Enable frame modulation for 6-bit panel (default 0): 1: enable frame modulation 0: disable frame modulation *also check register Control_B[5] and Control_B[7] Enable horizontal interpolation (default 0): 1: enable horizontal interpolation 0: disable horizontal interpolation Enable vertical interpolation (default 0): 1: enable vertical interpolation 0: disable vertical interpolation Enable horizontal rounding (default 0): 34 25H[7] 23H[7] 21H[7] 1FH[7] 1DH[7]
1
RW
15
RW
1
RW
15
RW
1
RW
15
RW
1
RW
15
RW
1
RW
15
RW
1
RW
Dithering Enable
1
RW
28H[7]
Frame Modulation Enable
1
RW
28H[6]
Horizontal Interpolation Enable Vertical Interpolation Enable Horizontal Rounding November, 1999 Revision B
1
RW
28H[5]
1
RW
28H[4]
1
RW
28H[3]
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Enable Vertical Rounding Enable Horizontal Table Lookup Enable Vertical Table Lookup Enable HSYNC Threshold Enable 1 RW
SD1210
1
RW
1
RW
1
RW
OSD Intensity
1
RW
Load ALL EEPROM Load Mode Dependent EEPROM CPU control enable
1 1
RW RW
1
RW
Status 0
8
R
Status 1
4
R
Control_A
8
RW
1: enable horizontal rounding 0: disable horizontal rounding 28H[2] Enable vertical rounding (default 0): 1: enable vertical rounding 0: disable vertical rounding 28H[1] Enable horizontal Table Lookup (default 0): 1: enable horizontal Table Lookup 0: disable horizontal Table Lookup 28H[0] Enable vertical Table Lookup (default 0): 1: enable vertical Table Lookup 0: disable vertical Table Lookup 29H[4] Enable detection of short lines (IBM panel only, default 0): 1: Enable such detection 0: disable such detection 29H[3] OSD intensity selection: 0: half intensity 1: full intensity 29H[2] Should be kept low most of the time. A high pulse will force SD1210 to reload all EEPROM entries 29H[1] Should be kept low most of the time. A high pulse will force SD1210 to reload mode dependent EEPROM entries 29H[0] External CPU control enable: 0: disable external CPU control. SD1210 can write control registers, but CPU only read control registers. 1: enable external CPU control. CPU can read/write control registers. SD1210 cannot write control registers 2AH Read only internal status registers: 1: indicate error status 0: indicate normal status Bit 0: EEPROM vertical lookup table loading Bit 1: EERPOM horizontal lookup table loading Bit 2: EEPROM mode dependent entries loading Bit 3: EEPROM calibration entries loading Bit 4: input has too few lines Bit 5: no input video Bit 6: input data clock is too fast Bit 7: refresh rate exceed LCD panel specification 2BH[3:0] Internal auto calibration state 0: Idle State 1-4: Loading EEPROM data 5-9: Frequency Calibration State (Auto Frequency Calibration will be done after state 9) 10: Phase Calibration State (Auto Phase Calibration will be done after state 10) 11: Adjust Horizontal Back Porch state 12: Phase Tracking state 2CH[7:0] Control Register A: 0 - disable 1 - enable default is 00H Bit 0: Horizontal Interpolation Offset Enable SmartASIC Confidential
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SD1210
Control_B
8
RW
Bit 1: Vertical Interpolation Offset Enable Bit 2: Horizontal Interpolation Fraction Reset Enable Bit 3: Vertical Interpolation Fraction Reset Enable Bit 4: Horizontal Interpolation Integer Increment Enable Bit 5: Vertical Interpolation Integer Increment Enable Bit 6: Single Pixel Output Mode Enable Bit 7: Disable "DE_OUT", for blanking screen purpose 2DH[7:0] Control Register B Bit [2:0]: Pixel Comparison Mode: 0: compare r even(default) 1: compare g even 2: compare b even 3: invalid 4: compare r odd 5: compare g odd 6: compare b odd 7: invalid *Using pixel comparison should program register "Pixel Comparison Value" and check register "Status 2[1:0]" Bit [4:3]: Brightness Control: 0: disable brightness control(default) 1: reduce brightness 2: increase brightness 3: invalid *Using brightness control should specify register "Brightness Adjustment" and check register "Status 2[2]" Bit [5]: Frame Modulation Mode: 0: 2-bit mode(default) 1: 1-bit mode Bit [6]: 6-bit Panel Rounding Enable: 0: disable(default) 1: enable Bit [7]: Frame Modulation Scheme Selection: 0: Scheme A(default) 1: Scheme B 2EH[7:0] Control Register C Bit [1:0]: Horizontal Interpolation Special Processing Mode: 0: disable 1: linear 2: replication(default) 3: invalid Bit [3:2]: Vertical Interpolation Special Processing Mode: 0: disable
Control_C
8
RW
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1: linear 2: replication(default) 3: invalid
SD1210
Bit [4]: OSD Transparency Enable: 0: disable(default) 1: enable *also need to program registers "OSD R Weight", "OSD G Weight" and "OSD B Weight" Bit [5]: Advanced Post Processing Enable: 0: disable(default) 1: enable *also need to specify registers "Advanced Processing R Weight", "Advanced Processing G Weight", "Advanced Processing B Weight" , "Advanced Processing R Value", "Advanced Processing G Value" and "Advanced Processing B Value" for properly functioning Bit [6]: Dithering Scheme Selection 0: Scheme A(default) 1: Scheme B Bit [7]: Reserved 2FH[7:0] Control Register D Bit [3:0]: Advanced Processing Shift Amount. From 0 - 8. 8 is the default value. Bit [4]: Advance Mixing Shift Enable 0: disable(default) 1: enable *This is a option for Advanced Post Processing Bit [7:5]: Reserved High Byte For Interpolation Horizontal Offset Default is 00H Low Byte For Interpolation Horizontal Offset Default is 00H High Byte For Interpolation Vertical Offset Default is 00H Low Byte For Interpolation Vertical Offset Default is 00H Bit [2:0]: High Bits For Horizontal Interpolation Reset Count. Default is 0H. Bit [7:3]: Reserved Low Byte For Horizontal Interpolation Reset Count. Default is 00H. Bit [1:0]: High Bits For Vertical Interpolation Reset Count. Default is 0H. Low Byte For Interpolation Vertical Reset Count. Default is 00H. Mixing Weight For OSD R. Default is 00H. Mixing Weight For OSD G. Default is 00H. 37
Control_D
8
RW
Interpolation H. Offset Interpolation H. Offset Interpolation V. Offset Interpolation V. Offset H. Interpolation Rest Count H. Interpolation Reset Count V. Interpolation Reset Count V. Interpolation Reset Count OSD R Weight OSD G Weight November, 1999 Revision B
8 8 8 8 8
RW RW RW RW RW
30H[7:0] 31H[7:0] 32H{7:0] 33H[7:0] 34H[7:0]
8 8 8 8 8
RW RW RW RW RW
35H[7:0] 36H[7:0] 37H[7:0] 38H[7:0] 39H[7:0]
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OSD B Weight Advanced Processing R Weight Advanced Processing G Weight Advanced Processing B Weight Advanced Processing R Value Advanced Processing G Value Advanced Processing B Value Brightness Adjustment Pixel Comparison Value Status 2 8 8 8 8 8 8 8 8 8 8 RW RW RW RW RW RW RW RW RW R
SD1210
3AH[7:0] Mixing Weight For OSD B. Default is 00H. 3BH[7:0] Weight For Advanced Post Processing R default is 00H 3CH[7:0] Weight For Advanced Post Processing G Default is 00H 3DH[7:0] Weight For Advanced Post Processing B Default is 00H 3EH[7:0] Value For Advanced Post Processing R Default is 00H 3FH[7:0] Value For Advanced Post Processing G Default is 00H 40H[7:0] Value For Advanced Post Processing B Default is 00H 41H[7:0] The Adjust Amount For Reducing/Increasing Brightness. Default is 00H. 42H[7:0] The Value To Compare The Incoming Pixel Data. Default is 00H. 43H[7:0] The Status Register 2 Bit [1:0]: Result for comparing the selected incoming pixel with "Pixel Comparison Value": 0: invalid 1: incoming pixel > "Pixel Comparison Value" 2: incoming pixel = "Pixel Comparison Value" 3: incoming pixel < "Pixel Comparison Value" Bit [2]: Status for brightness control 0: Normal, no underflow/overflow 1: brightness reduced too much causes underflow/increased too much causes overflow Bit [7:3]: Reserved Clock Recovery Control Register: Default value is 71H Bit 0: clock frequency is divisible by 2 Bit 1: clock frequency is divisible by 4 Bit 2: clock frequency is divisible by 8 Bit 3: enable phase tracking feature Bit 4: enable auto phase calibration Bit 5: enable auto frequency calibration Bit 6: enable auto mode detection Bit 7: enable operation at half clock speed Offset value added to the calibrated phase when phase tracking occurs Number of frames waited before phase tracking occurs 0: Normal phase calibration (default) 1: Final phase = phase total - phase offset 0: Disable auto phase total calculation 1: Enable auto phase total calculation (default) 0: Uses the external incoming SYNC signals (default) 1: Allow the use of the default SYNC signals instead of the incoming SYNC signals 38
Recovery Control
8
RW
44H
Phase Range Phase Track Waiting Time Quick Phase Enable PWM Enable Standalone Enable
4 24 1 1 1
RW RW RW RW RW
45H 46H 48H 49H[0] 49H[1] 49H[2]
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Digital Enable Phase Offset Phase Total Image Quality Index 1 10 10 30 RW RW RW R 49H[3] 4AH 4BH 4CH 4DH 4EH[5:0],4 FH, 50H, 51H 52H[7:0]
SD1210
0: Analog interface (default) 1: Digital interface (no auto calibration) Offset value subtracted from phase total when doing quick phase calculation User defined value for a particular frequency Read only register for CPU to monitor Image Quality Index. The Image Quality Index is used by auto phase calibration. Text-Enhancement Control Bit[0]: text enhancement enable 0: disable 1: enable Bit[1]: Reserved Bit[6:2]: text-enhanced level Level 0 - 14. Level "0" is the same as original source, and "14" is the highest enhancement level. Bit[7]: Reserved
Text Control
8
RW
Sharpness Control
8
RW
Default is 00H 53H[7:0] Sharpness-Enhancement Control Bit[0]: sharpness enhancement enable 0: disable 1: enable Bit[1]: Reserved Bit[6:2]: sharpness-enhanced level Level 1 - 19. Level "5" is the same as the original source. From "4" to "1" intend to soften the picture, and "1" is the softest level. From level "6" to "19" will sharpen the picture gradually. Level "19" is the sharpest output. Bit[7]: Reserved Default is 14H 54H[7:0] Control Register E Bit[3:0]: text enhancement threshold. Bit[4]: reserved Bit[6:5]: Frame Modulation Mode 0: compatible with SD1210 1-3: new schemes Bit[7]: reserved Default is 05H
Control_E
8
RW
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Pixel_h Pixel_v Pixle_out Fc3_start Channel_select 11 11 24 1 1 RW RW R RW RW 55H[10:8] 56H[7:0] 57H[10:8] 58H[7:0] 59H, 5AH, 5BH 5CH[4] 5CH[3]
SD1210
The x location for reading "Pixel_out" register The y location for reading "Pixel_out" register Read out pixel located by "Pixel_h" and "Pixel_v"
Dual_pixel Soft_start ICS_phase_state Hsize_by842_en
1 1 1 1
RW RW RW RW
Video_mode Input_yuv Yuv_signed decimation
1 1 1 1
RW RW RW RW
Detect_en
2
RW
Agc_en Agc_gain_red Agc_gain_green Agc_gain_blue Agc_offset_red Agc_offset_green Agc_offset_blue Input_max Input_min ICS_freq_state ICS_hsize_valid ICS_iq_valid IQ_valid Divisor_valid
1 8 8 8 8 8 8 8 8 1 1 1 1 1
RW RW RW RW RW RW RW R R RW RW RW RW RW
Forces auto calibration to recalculate h back porch Only for single pixel input 0: takes input data from channel 1 1: takes input data from channel 0 5CH[2] 0: takes input data from one single channel 1: takes input data from both channels 5CH[1] Restarts auto calibration without going into reset 5CH[0] Forces auto calibration to calculate the image quality for a particular clock phase when supplied by ics chips 5DH[7] Turn on internal hsize matching by8, 4, 2 when clock frequency calibration is done by8, 4, 2. Used mainly for special non-full screen inputs. 5DH[6] 0: disable input video mode 1: input is video 5DH[5] 0: input video format is RGB 1: input video format is YUV 4:2:2 5DH[4] 0: input video YUV format is unsigned 1: input video YUV format is signed 5DH[3] Used when input resolution is higher than output 1: enable special decimation control 0: disable special decimation 5DH[2:1] Input data range detection. The results are put in register 64H and 65H 0: disable detection 1: detect MAX/MIN using R color 2: detect MAX/MIN using G color 3: detect MAX/MIN using B color 5DH[0] Automatic gain control enable 5EH Gain amount for R color 5FH Gain amount for G color 60H Gain amount for B color 61H Offset amount for R color 62H Offset amount for G color 63H Offset amount for B color 64H Detected maximum input data (please see 5DH) 65H Detected minimum input data (please see 5DH) 66H[5] Forces auto calibration to calculate the hsize value for a particular clock frequency when supplied by ics chips 66H[4] Indicates when hsize value is ready for cpu to read in ics mode. Can be clear by cpu 66H[3] Indicates when image quality is ready for cpu to read in ics mode. Can be clear by cpu 66H[2] Indicates when image quality is ready for cpu to read in Regular non-ics mode. Can be clear by cpu 66H[1] Indicates when auto clock frequency calibration is done and frequency value is ready for cpu to read. Can be clear by cpu 40
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Non_full_screen Divisor_value IQ_value 1 11 30 RW R R 66H[0]
SD1210
Panel_on
1
RW
Indicates when input data is non full screen. Can be clear by cpu 67H[2:0], Read only register containing value of clock frequency 68H when divisor_valid is asserted 69H[5:0], Read only register containing value of image quality 6AH,6BH, when either ics_iq_valid or iq_valid is asserted 6CH 6DH[0] 1: turn on all the outputs to the panel 0: disable outputs to the panel (need to disable EEPROM 265H[3], 266H[7], 266H[3], 267H[7], 267H[3] to get complete output disable). 6EH[2:0], Read only register containing value of hsize when 6FH ics_hsize_valid is asserted 70H[5:0] Divisor value use to divide fast pwm_free_clk to slower free_clk
ICS_hsize_value Rom_clk_sel
11 6
R RW
3.7.
Control Flow
When SD1210 is powered up, the reference system and SD1210 will perform the following functions in sequence: 1. System will generate a Power-On Reset to SD1210. 2. Once the SD1210 receives the Reset, SD1210 will load the contents of EEPROM and start the auto-calibration process. 3. In the meantime, the external CPU can change the contents of the control registers of the SD1210. If necessary, the external CPU can send an additional Reset to restart the whole process.
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SD1210
4. ELECTRICAL SPECIFICATIONS
This section presents the electrical specifications of the SD1210.
4.1.
Symbol VCC Vin Vout VCC5 Vin5 Vout5 TSTG
Absolute Maximum Ratings
Parameter Power Supply Input Voltage Output Voltage Power Supply for 5V Input Voltage for 5V Output Voltage for 5V Storage Temperature Rating -0.3 to 3.6 -0.3 to VCC + 0.3 -0.3 to VCC +0.3 -0.3 to 6.0 -0.3 to VCC5 + 0.3 -0.3 to VCC5 +0.3 -55 to 150 Units V V V V V V C
4.2.
Symbol VCC Vin VCC5 VIN5 TJ
Recommended Operating Conditions
Parameter Power Supply Input Voltage Commercial Power Supply for 5V Input Voltage for 5V Commercial Junction Operating Temperature Min. 3.0 0 4.75 0 0 Typ. 3.3 5.0 25 Max. 3.6 VCC 5.25 VCC5 115 Units V V V V C
4.3.
Symbol IIL IOZ CIN3 COUT3 CBID3 CIN5 COUT5 CBID5
General DC Characteristics
Parameter Input Leakage Current TRI-state Leakage Current 3.3V Input Capacitance 3.3V Output Capacitance 3.3V Bi-directional Buffer Capacitance 5V Input Capacitance 5V Output Capacitance 5V Bi-directional Buffer Capacitance Conditions no pull - up or pull - down Min. -1 -1 2.8 2.7 2.7 2.8 2.7 2.7 5.6 5.6 4.9 4.9 Typ. Max. 1 1 Units A A F F F F F F
Note: The capacitance above does not include PAD capacitance and package capacitance. One can estimate pin capacitance by adding pad capacitance, which is about 0.5 F, and the package capacitance
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SD1210
4.4.
Symbol VIL VIH VT-
DC Electrical Characteristics for 3.3 V Operation
Parameter Input low voltage Input high voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up /down resistance Conditions CMOS CMOS COMS Min. 0.7*VCC 1.20 Typ. Max. 0.3*VCC Units V V V
(Under Recommended Operation Conditions and VCC = 3.0 ~ 3.6V, TJ = 0C to +115C)
VT+
COMS
2.10
V
VOL VOH RI
IOH=2,4,8,12, 16,24 mA IOH=2,4,8,12, 16,24 mA VIL=0V or VIH=VCC
0.4 2.4 75
V V K
4.5.
Symbol VIL VIH VIL VIH VTVT+
DC Electrical Characteristics for 5V Operation
Parameter Input low voltage Input high voltage Input low voltage Input high voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Output high voltage Input pull-up / down resistance Conditions COMS COMS TTL TTL CMOS COMS Min. 0.7*VCC 0.8 2.0 1.78 3.00 Typ. Max. 0.3*VCC Units V V V V V V
(Under Recommended Operation Conditions and VCC=4.75~5.25,TJ=0C to +115C)
VTVT+
TTL TTL
1.10 1.90
V V
VOL VOH RI
IOL=2,4,8,16,24mA IOH=2,4,8,16,24 mA VIL=0V or VIH=VCC
0.4 3.5 50
V V K
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SD1210
5. PACKAGE DIMENSIONS
160
1
120
160 PQFP (28x28 mm)
E HE
40
D HD
80
A
A2 A1
c
b
e
L L1 November, 1999 Revision B SmartASIC Confidential
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SD1210
Symbol\Unit A A1 A2 b c D E e HD HE L L1
Inch (Base) 0.154 (Min) - 0.160(Max) 0.010 (Min) 0.127 +/-0.003 0.010 (Min) - 0.014(Max) .005 (Min) - 0.009 (Max) 1.102+/-0.002 1.102+/-0.002 0.026 (Ref) 1.228 +/- 0.01 1.228 +/- 0.01 0.031+/-0.006 0.063(Ref) 0 - 7.0
MM (Base) 3.92 (Min) - 4.06 (Max) 0.25 (Min) 3.22 +/- 0.08 0.25(Min) - 0.35(Max) 0.13(Min) - 0.25(Max) 28.000+/-0.10 28.000+/-0.10 0.65 (Ref) 31.20 +/- 0.25 31.20 +/- 0.25 0.80+/-0.15 1.60(Ref) 0 - 7.0
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SD1210
6. ORDER INFORMATION
Order Code SD1210
Temperature Commercial 0C ~ 70C
Package 160-pin PQFP 28 x 28 (mm)
Speed 100MHz
SmartASIC, Inc.
U.S.A. & Europe 525 Race St. Suite 250 San Jose, CA 95126 U.S.A. Tel : 1-408-283-5098 Fax : 1-408-283-5099
WORLDWIDE OFFICES
Asia Pacific 3F, No. 68, Chou-Tze St. Nei-Hu Dist. Taipei 114, Taiwan R.O.C. Tel : 886-2-8797-7889 Fax : 886-2-8797-6829
@Copyright 1999, SmartASIC, Inc.
This information in this document is subject to change without notice. SmartASIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. SmartASIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
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